Field of the Invention
The invention relates to control of access to a shared resource and, in particular, to a complex-memory-core priority and arbitration scheme to enhance burst performance to and from a common (shared) hardware resource, e.g., DRAM, arbitrating multiple bus devices supporting DMA (direct memory access), including bus devices supporting real-time data transfers, to one memory resource control and data path.
The invention further relates to a priority architecture that allows for the determination of latency and bandwidth requirements of all supported bus devices, and the storing of the results in hardware registers. The registers are programmable, and may be changed based on bandwidth requirements, e.g., a change in video resolution or for enabling a faster SCSI device on a PCI bus.